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(R)
X9260
Dual Supply/Low Power/256-Tap/SPI bus
Data Sheet August 29, 2006 FN8170.3
Dual Digitally-Controlled (XDCPTM) Potentiometers
FEATURES * Dual-Two Separate Potentiometers * 256 Resistor Taps/pot-0.4% Resolution * SPI Serial Interface for Write, Read, and Transfer Operations of the Potentiometer * Wiper Resistance, 100 typical @ V+ = 5V, V- = -5V * 4 Nonvolatile Data Registers for Each Potentiometer * Nonvolatile Storage of Multiple Wiper Positions * Power-on Recall. Loads Saved Wiper Position on Power-up. * Standby Current <5A Max * VCC: 2.7V to 5.5V Operation * 50k, 100k Versions of End to End Resistance * 100 yr. Data Retention * Endurance: 100,000 Data Changes per Bit per Register * 24 Ld SOIC * Low Power CMOS * Power Supply VCC = 2.7V to 5.5V V+ = 2.7V to 5.5V V- = -2.7V to -5.5V * Pb-Free Plus Anneal Available (RoHS Compliant) FUNCTIONAL DIAGRAM
VCC V+
DESCRIPTION The X9260 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nononvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default Data Register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
RH0
RH1
SPI Bus Interface
Address Data Status
Write Read Transfer Inc/Dec Bus Interface and Control Control
Power-on Recall Wiper Counter Registers (WCR) Data Registers (DR0-DR3)
VSS
V-
RW0
RL0
RW1
RL1
50k or 100k versions
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners
X9260 Ordering Information
PART NUMBER X9260TS24I X9260TS24IZ (Note) X9260US24 X9260US24Z (Note) X9260TS24I-2.7 PART MARKING X9260TS I X9260TS ZI X9260US X9260US Z X9260TS G 2.7 to 5.5 100 50 POTENTIOMETER ORGANIZATION TEMPERATURE (k) RANGE (C) VCC LIMITS (V) 5 10% 100 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 50 0 to +70 0 to +70 PACKAGE 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) PKG. DWG. # M24.3 M24.3 M24.3 M24.3 M24.3 M24.3 M24.3 M24.3
X9260TS24IZ-2.7 (Note) X9260TS ZG X9260US24-2.7 X9260US F
X9260US24Z-2.7 (Note) X9260US ZF *Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DETAILED FUNCTIONAL DIAGRAM
RH0 RL0 RW0 VCC V+ Power-on Recall HOLD CS SCK SO SI A0 A1 INTERFACE AND CONTROL CIRCUITRY 8 WP Data Power-on Recall R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 1 R0 R1 Wiper Counter Register (WCR) Pot 0
R2 R3
50K and 100K 256-taps
R2 R3
VSS
V-
RL1 RH1 RW1
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CIRCUIT LEVEL APPLICATIONS * Vary the gain of a voltage amplifier * Provide programmable dc reference voltages for comparators and detectors * Control the volume in audio circuits * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS * Adjust the contrast in LCD displays * Control the power level of LED transmitters in communication systems * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems PIN CONFIGURATION
SOIC SO A0 NC NC NC V+ VCC RL0 RH0 RW0 CS WP 1 2 3 4 5 6 7 8 9 10 11 12 X9260 24 23 22 21 20 19 18 17 16 15 14 13 HOLD SCK NC NC NC VVSS RW1 RH1 RL1 A1 SI
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PIN ASSIGNMENTS Pin (SOIC)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Symbol
SO A0 NC NC NC V+ VCC RL0 RH0 RW0 CS WP SI A1 RL1 RH1 RW1 VSS VNC NC NC SCK HOLD Serial Data Output for SPI bus Device Address for SPI bus. No Connect. No Connect. No Connect. Analog Supply Voltage (Positive) System Supply Voltage Low Terminal for Potentiometer 0. High Terminal for Potentiometer 0.
Function
Wiper Terminal for Potentiometer 0. Device Address for SPI bus. Hardware Write Protect Serial Data Input for SPI bus Device Address for SPI bus. Low Terminal for Potentiometer 1. High Terminal for Potentiometer 1. Wiper Terminal for Potentiometer 1. System Ground Analog Supply Voltage (Negative) No Connect No Connect No Connect Serial Clock for SPI bus Device select. Pause the SPI serial bus.
PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9260.
HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the 4-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9260. CHIP SELECT (CS) When CS is HIGH, the X9260 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the
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standby state. CS LOW enables the X9260, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RH and RL such that RH0 and RL0 are the terminals of POT 0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RW such that RW0 is the terminals of POT 0 and so on. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Analog Supply Voltages (V+ and V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins NO CONNECT No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. PRINCIPLES OF OPERATION Serial Interface The X9260 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9260 is comprised of a resistor array (See Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (See Table 1). Power-up and Down Requirements. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. During powerup and power-down, VCC, V+, and V- must reach their final values within 1msecs of each other. The VCC ramp rate spec is always in effect.
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Figure 1. Detailed Potentiometer Block Diagram
One of Two Potentiometers SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) 8 REGISTER 1 (DR1) 8 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) INC/DEC LOGIC UP/DN MODIFIED SCK UP/DN CLK RL SERIAL BUS INPUT C O U N T E R D E C O D E RH
REGISTER 2 (DR2)
REGISTER 3 (DR3)
IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH
RW
DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9260 contains two Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (See Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9260 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR.
Data Registers (DR) Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0~255). Status Register (SR) This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only. - When WIP = 1, indicates that high-voltage write cycle is in progress. - When WIP = 0, indicates that no high-voltage write cycle is in progress.
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Table 5. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7 V (MSB) WCR6 V WCR5 V WCR4 V WCR3 V WCR2 V WCR1 V WCR0 V (LSB)
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7 NV MSB Bit 6 NV Bit 5 NV Bit 4 NV Bit 3 NV Bit 2 NV Bit 1 NV Bit 0 NV LSB
DEVICE DESCRIPTION Instructions IDENTIFICATION BYTE ( ID AND A ) The first byte sent to the X9260 from the host, following a CS going HIGH to LOW, is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9260; this is fixed as 0101[B] (refer to Table 3). The AD[3:0] bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A3 - A0 input pins. The slave address is externally specified by the user. The X9260 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9260 to successfully continue the Table 3. Identification Byte Format
Device Type Identifier
command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE ( I[3:0] ) The next byte sent to the X9260 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least significant bit points to one of two Wiper Counter Registers or Pots.The format is shown below in Table 4.
Slave Address
ID3 0 (MSB)
ID2 1
ID1 0
ID0 1
A3
A2
A1
A0 (LSB)
Table 4. Instruction Byte Format
Instruction Opcode Data Register Selection Pot Selection (WCR Selection)
I3 (MSB)
I2
I1
I0
RB
RA
0
P0 (LSB)
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DEVICE DESCRIPTION Instructions Four of the ten instructions are three bytes in length. These instructions are: - Read Wiper Counter Register - read the current wiper position of the selected potentiometer, - Write Wiper Counter Register - change current wiper position of the selected potentiometer, - Read Data Register - read the contents of the selected Data Register; - Write Data Register - write a new value to the selected Data Register. - Read Status - This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 5). Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9260; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: - XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the associated Wiper Counter Register. - XFR Wiper Counter Register to Data Register - This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. - Global XFR Data Register to Wiper Counter Register - This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. - Global XFR Wiper Counter Register to Data Register - This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (See Figures 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9260 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown. See Instruction format for more details.
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Figure 2. Two-Byte Instruction Sequence
CS SCK
SI
0
1
0
1
0 0
0 0 A1 A0 I3 I2 I1 I0 RB RA
0 P0
ID3 ID2 ID1 ID0 Device ID
Internal Address
Instruction Opcode
Register Pot/WCR Address Address
Figure 3. Three-Byte Instruction Sequence (Write)
CS SCL SI 0 1 0 1 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA 0 P0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register Bit [7:0]
ID3 ID2 ID1 ID0 Device ID
Instruction Opcode
Register Pot/WCR Address Address
Figure 4. Three-Byte Instruction Sequence (Read)
CS SCL SI 0 1 0 1 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA X P0 X X X X
0
X
X
X
ID3 ID2 ID1 ID0 Device ID
Don't Care
Instruction Opcode
Register Pot/WCR Address Address
S0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register Bit [7:0]
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Figure 5. Three-Byte Instruction Sequence (Read Status Register)
CS SCL SI 0 1 0 1 0 0 0 0 A1 A0 Internal Address 1 I3 0 I2 1 1 RB RA 0 P0 0 0 0 0 0 0 0 WIP Status Bit
ID3 ID2 ID1 ID0 Device ID
I1 I0
Instruction Opcode
Register Pot/WCR Address Address
Figure 6. Increment/Decrement Instruction Sequence
CS SCL SI 0 1 0 1 0 0 0 0 A1 A0 Internal Address I2 I3 I1 I0 RB RA 0 P0 I N C 1 I N C 2 I N C n D E C 1 D E C n
ID3 ID2 ID1 ID0 Device ID
Instruction Opcode
Register Pot/WCR Address Address
Figure 7. Increment/Decrement Timing Limits
tWRID SCK
SI
R W
VOLTAGE OUT INC/DEC CMD ISSUED
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Table 5. Instruction Set Instruction
Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register
Note: 1/0 = data is one or zero
I3 1
1 1 1 1 1 0 1
I2 0
0 0 1 1 1 0 0
Instruction Set I1 I0 RB RA 0 1 0 0
1 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1/0 1/0 1/0 1/0 1/0 1/0 0 1/0 1/0 1/0 1/0 1/0 1/0
0 0
0 0 0 0 0 0 0
P0
1/0 1/0 1/0 1/0 1/0 1/0 0 0
Operation
Read the contents of the Wiper Counter Register pointed to by P0 Write new value to the Wiper Counter Register pointed to by P0 Read the contents of the Data Register pointed to by P0 and RB - RA Write new value to the Data Register pointed to by P0 and RB - RA Transfer the contents of the Data Register pointed to by P0 and RB - RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P0 to the Data Register pointed to by RB - RA Transfer the contents of the Data Registers pointed to by RB - RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB - RA of all four pots Enable Increment/decrement of the Control Latch pointed to by P0
0
0
1
0
0
0
0
1/0
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INSTRUCTION FORMAT Read Wiper Counter Register (WCR)
Device Type Identifier 0 1 0 1 Device Addresses Instruction Opcode 0 0 1 WCR Addresses 0 0 Wiper Position (Sent by X9260 on SO) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1
CS Falling Edge
0 0 A1 A0 1
W C 0 P0 R 7
CS W Rising C Edge R 0
Write Wiper Counter Register (WCR)
Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 1 0 0 WCR Addresses 0 W C 0 P0 R 7 Data Byte (Sent by Host on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1
CS Falling Edge 0
0 0 A1 A0 1
CS W Rising C Edge R 0
Read Data Register (DR)
Device Type Device Instruction DR and WCR Data Byte CS CS Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA 0 P0 D D D D D D D D Edge 76543210
Write Data Register (DR)
HIGH-VOLTAGE WRITE CYCLE
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CS Falling Edge 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA
Device Type Identifier
Device Addresses
Instruction Opcode
DR and WCR Addresses 0
CS Rising D D D D D D D D Edge P0 76543210
Data Byte (Sent by Host on SI)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses 0 CS Rising 0 A1 A0 0 0 0 1 RB RA 0 0 Edge Instruction Opcode DR Addresses
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Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type Device Instruction DR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 0 0 RB RA 0 0 Edge HIGH-VOLTAGE WRITE CYCLE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type Device Instruction DR and WCR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 1 1 0 RB RA 0 P0 Edge HIGH-VOLTAGE WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type Device Instruction DR and WCR CS CS Identifier Addresses Opcode Addresses Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 1 0 1 RB RA 0 P0 Edge
Increment/Decrement Wiper Counter Register
Device Type Device Instruction WCR Increment/Decrement CS CS Identifier Addresses Opcode Addresses (Sent by Master on SDA) Falling Rising Edge 0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 P0 I/D I/D . . . . I/D I/D Edge
(WCR) Read Status Register (SR)
Device Type Device Instruction WCR Data Byte CS Identifier Addresses Opcode Addresses (Sent by X9260 on SO) Falling Edge 0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP CS Rising Edge
Notes: (1) (2) (2) (3)
"A1 ~ A0": stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). "D": stands for the decrement operation, SI held LOW during active SCK phase (high).
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ABSOLUTE MAXIMUM RATINGS Temperature under bias ........................ -65 to +135C Storage temperature ............................. -65 to +150C Voltage on SCK, SCL or any address input with respect to VSS ................................. -1V to +7V Voltage on V+ (referenced to VSS)........................ 10V Voltage on V- (referenced to VSS)........................-10V (V+) - (V-) .............................................................. 12V Any VH/RH ..............................................................V+ Any VL/RL.................................................................VLead temperature (soldering, 10 seconds) ...... +300C IW (10 seconds)..................................................6mA COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0C -40C Max. +70C +85C Device X9260 X9260-2.7
V+ V-
Supply Voltage (VCC)(4) Limits 5V 10% 2.7V to 5.5V
2.7V to 5.5V -2.5V to -5.5V
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POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter
End to end resistance Power rating IW RW RW Vv+ VvVTERM Wiper current Wiper resistance Wiper resistance Voltage on V+ pin Voltage on V- pin X9260 X9260-2.7 X9260 X9260-2.7 Voltage on any VH/RH or VL/RL pin Noise Resolution (4) Absolute linearity (1) Relative linearity (2) Temperature coefficient Ratiometric Temperature Coefficient CH/CL/CW Potentiometer Capacitances 10/10/25 300 20 +4.5 +2.7 -5.5 -5.5 V-120 0.4 1 0.6
Min.
Typ.
Max.
20 50 3 250 150 +5.5 +5.5 -4.5 -2.7 V+
Unit
% mW mA V V V dBV % MI(3) MI(3) ppm/C ppm/C pF
Test Conditions
25C, each pot Wiper current = 1mA, V+ = 3V; V- = -3V Wiper current = 1mA, V+ = 3V; V- = -3V
Ref: 1kHz Vw(n)(actual) - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI]
See Circuit #3
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power-up VCC > VH, VL, and VW. (5) n = 0, 1, 2, ...,255; m =0, 1, 2, ..., 254.
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH
Parameter
VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage
Min.
Typ.
Max.
400
Units
A mA A A A V V V V V IOL = 3mA
Test Conditions
fSCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V VIN = VSS to VCC VOUT = VSS to VCC
1
5 5 10 10
VCC x 0.7 -1 VCC - 0.8 VCC - 0.4
VCC + 1 VCC x 0.3 0.4
IOH = -1mA, VCC +3V IOH = -0.4mA, VCC +3V
ENDURANCE AND DATA RETENTION Parameter
Minimum endurance Data retention
Min.
100,000 100
Units
Data changes per bit per register years
CAPACITANCE Symbol
CIN(6) COUT
(6)
Test
Output capacitance (SO) Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK)
Max.
8 6
Units
pF pF
Test Conditions
VOUT = 0V VIN = 0V
POWER-UP TIMING Symbol
tr VCC
(6)
Parameter
VCC Power-up rate Power-up to initiation of read operation
Min.
0.2
Max.
50 1
Units
V/ms ms
tPUR(7)
POWER-UP AND DOWN REQUIREMENTS The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The VCC ramp rate spec is always in effect. A.C. TEST CONDITIONS Input Pulse Levels
Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are not 100% tested.
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EQUIVALENT A.C. LOAD CIRCUIT
5V 1462 SO pin 2714 100pF SO pin 1217 100pF 10pF RW 3V 1382 RH CL CW 25pF CL 10pF
SPICE MACROMODEL
RTOTAL RL
AC TIMING Symbol
fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI clock frequency SSI/SPI clock cycle rime SSI/SPI clock high rime SSI/SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 setup time WP, A0 hold time 2 0 0 400 100 100 100 100 10 0 100 100 0 500 200 200 250 250 50 50 2 2 250 200
Parameter
Min.
Max.
2
Units
MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns s ns ns
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FN8170.3 August 29, 2006
X9260
HIGH-VOLTAGE WRITE CYCLE TIMING Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
5
Max.
10
Units
ms
XDCP TIMING Symbol
tWRPO tWRL
Parameter
Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions)
Min.
5 5
Max. Units
10 10 s s
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
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FN8170.3 August 29, 2006
X9260
TIMING DIAGRAMS Input Timing
tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG
tFI LSB
tRI
SO
High Impedance
Output Timing
CS
SCK tV SO MSB tHO
... ... LSB
tDIS
SI
ADDR
Hold Timing
CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH ...
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FN8170.3 August 29, 2006
X9260
XDCP Timing (for All Load Instructions)
CS
SCK
... MSB ...
tWRL LSB
SI
VWx
SO
High Impedance
Write Protect and Device Address Pins Timing
CS WP A0 A1 tWPASU
(Any Instruction) tWPAH
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APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers
VR +VR
RW
I
THREE- TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER
TWO-TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT
Application Circuits
NONINVERTING AMPLIFIER VOLTAGE REGULATOR
VS
+ - VO VIN 317 R1 R2 R1 Iadj R2 VO (REG)
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERISIS
R1 VS 100k - +
R2
VS
- +
VO
VO } } TL072 R1 R2
10k 10k +12V 10k -12V
VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min)
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FN8170.3 August 29, 2006
X9260
Application Circuits (continued)
ATTENUATOR FILTER
C R1 VS R3 R4 R1 = R2 = R3 = R4 = 10k R1 R2 - + VO VS R R2 + - VO
V O = G VS -1/2 G +1/2
GO = 1 + R2/R1 fc = 1/(2RC)
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R1
R2
}
VS
}
- +
C1 VO VS
R2 + -
V O = G VS G = - R2/R1
ZIN
R1 R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2
FUNCTION GENERATOR
C
- +
R2
R1 - +
} RA } RB
frequency R1, R2, C amplitude RA, RB
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FN8170.3 August 29, 2006
X9260 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8 Rev. 1 4/06
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0 8 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 23
FN8170.3 August 29, 2006

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